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m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 1 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. based on ddr 3 - 1 066 /1333 /1600 256 mx 8 (2gb/4gb) sdram b - die features ?performance: speed sort pc 3 - 8500 pc 3 - 10600 pc3 - 12800 unit - be - cg - d i dimm cas latency 7 9 11 fck C C C ? 2 40 - pin dual in - line memory module ( u dimm) ? 256mx 64 (2gb) / 512mx64 (4gb) ddr 3 unbuffered dimm based on 256 mx 8 ddr 3 sdram b - die devices . ? intended for 533 mhz /667mhz /800mhz applications ? inputs and outputs are s stl - 1 5 compatible ? v dd = v ddq = 1. 5 v ? 0.075 v ? sdrams have 8 internal banks for concurrent operation ? differential clock inputs ? data is read or written on both clock edges ? dram dll aligns dq and dqs transitions with clock t ransitions. ? address and control signals are fully synchronous to positive clock edge ? nominal and dynamtic on - die termination support ? halogen free product ? programmable operation: - dimm ??? latency: 6 ,7,8 ,9 ,10,11 - burst type: sequential or interleave - burst length: bc 4, bl 8 - operation: burst read and write ? two different termination values (rtt_nom & rtt_wr) ? 1 5 /10/ 1 (row/column/rank) addressing for 2gb ? 1 5 /10/ 2 (row/column/rank) addressing for 4 gb ? extended operating temperature rage ? auto self - refresh option ? s erial presence detect ? gold contacts ? 2gb /4gb sdrams are in 78 - ball bga package ? rohs compliance and halogen free description m2f2g64cb88b7n / m2f4g64cb8hb5n / M2F2G64CB88BHN / m2f4g64cb8hb9n are 240 - pin double data rate 3 (d dr 3 ) synchronous dram unbuffered dual in - line memory module ( udimm ), organized as one rank of 256mx 64 (2gb) and two ranks of 512 mx 64 ( 4 gb) high - speed memory array. modules use eight 256 mx8 (2gb) 78 - ball bga packaged devices and sixteen 256mx8 (4gb) 78 - ball bga packaged devices . these dimms are manufactured using raw cards developed for broad industry use as reference designs. the use of these common design files minimizes electrical variation between suppliers. all elixir ddr 3 sdram dimms provide a high - per formance, flexible 8 - byte interface in a 5.25 long space - saving footprint. the dimm is intended for use in applications operating of 533 mhz /667mhz /800mhz clock speeds and achieves high - speed data transfer rates of 1066 mbps /1333mbps /1600mbps . prior to any access operation, the device ??? latency and burst /length/operation type must be programmed into the dimm by address inputs a0 - a14 ( 2gb/ 4gb) and i/o inputs ba0~ ba 2 using the mode register set cycle. the dimm uses serial presence - detect implemented via a serial eeprom using a standard iic protocol . the first 128 bytes of s pd data are programmed and locked during module assembly. the remaining 128 bytes are available for use by the customer. ordering information
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 2 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. part number speed organization power leads note m2f2g64cb88b7n - be d dr 3 - 1066 pc 3 - 85 00 533 mhz ( 1.875ns @ cl = 7 ) 256 mx64 1. 5 v gold m2f2g64cb88b7n - cg ddr3 - 1333 pc3 - 10600 667mhz ( 1.5ns @ cl = 9 ) m2 f 2g64cb88b7n - d i ddr3 - 1600 pc3 - 12800 800mhz (1.25ns @ cl = 11 ) m2f 4 g64cb8 h b 5 n - be ddr 3 - 1066 pc 3 - 85 00 533 mhz ( 1.875ns @ c l = 7 ) 512mx64 m2f 4 g64cb8 h b 5 n - cg ddr3 - 1333 pc3 - 10600 667mhz ( 1.5ns @ cl = 9) m2 f 4 g64cb8 h b 5 n - d i ddr3 - 1600 pc3 - 12800 800mhz (1.25ns @ cl= 11 ) m2f2g64cb88b h n - be ddr 3 - 1066 pc 3 - 85 00 533 mhz ( 1.875ns @ cl = 7 ) 256 mx64 m2f2g64cb88b h n - cg ddr3 - 1333 pc3 - 10600 667mhz ( 1.5ns @ cl = 9) m2 f 2g64cb88b h n - d i ddr3 - 1600 pc3 - 12800 800mhz (1.25ns @ cl= 11 ) m2f 4 g64cb8 h b 9 n - be ddr 3 - 1066 pc 3 - 85 00 533 mhz ( 1.875ns @ cl = 7 ) 512mx64 m2f 4 g64cb8 h b 9 n - cg ddr3 - 1333 pc3 - 10600 667mhz ( 1.5ns @ cl = 9) m2 f 4 g6 4cb8 h b 9 n - d i ddr3 - 1600 pc3 - 12800 800mhz (1.25ns @ cl= 11 ) pin description pin name description pin name description ck0 , ck1 clock inputs, positive line dq0 - dq63 data input/output ??? , ??? clock inputs, negative line dqs0 - dqs8 d ata strobes cke0 , c ke1 clock enable ???? - ???? data strobes complement ??? row address strobe dm0 - dm8 data masks ??? column address strobe ????? ? temperature event pin ?? write enable ????? ? reset pin ?? , ?? chip selects v ref dq , v ref ca input/output reference a0 - a9, a1 1, a 13 - a15 address inputs v ddspd spd and temp sensor power a10/ap address input/auto - p recharge sa0, sa1 serial presence detect address inputs a1 2 / ?? address input/ burst chop vtt termination voltage ba0 - ba2 sdram bank address inputs v ss ground odt0, odt1 a ctive termination control lines v dd core and i/o power scl serial presence detect clock input nc no connect sda serial presence detect data input/output
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 3 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ddr3 sdram pin assignment pin front pin back pin front pin back pin front pin back pin front pin back 1 v refdq 121 v ss 31 dq25 151 v ss 61 a2 181 a 1 91 dq41 211 v ss 2 v ss 122 dq4 32 v ss 152 dm3 ,dqs12,t dqs12 62 v dd 182 v dd 92 v ss 212 dm5, dqs14, tdqs14 3 dq0 123 dq5 33 ???? 1 5 3 nc , ?????? ? ?????? 63 ck1 , nc 183 v dd 93 ???? 213 nc , ???? ? , ????? ? 4 dq1 124 v ss 34 dq s3 154 v ss 64 ??? , nc 184 ck0 94 dqs5 214 v ss 5 v ss 125 dm0 ,dqs9, tdqs9 35 v ss 155 dq30 65 v dd 185 ??? ? 95 v ss 215 dq46 6 ???? ? 126 nc , ????? ? ????? 36 dq26 156 dq31 66 v dd 186 v dd 96 dq42 216 dq47 7 dqs0 127 v ss 37 dq27 157 v ss 67 v refca 187 ????? , nc ? 97 dq43 217 v ss 8 v ss 128 dq6 38 v ss 158 cb4, nc 68 p ar _i n , nc 188 a0 98 v ss 218 dq52 9 dq2 129 dq7 39 cb0, nc 159 cb5, nc 69 v dd 189 v dd 99 dq48 219 dq53 10 dq3 130 v ss 40 cb1, nc 160 v ss 70 a10/ap 190 ba1 100 dq 49 220 v ss 11 v ss 131 dq12 41 v ss 161 dm8 ,dqs17, tdqs17,nc 71 ba0 191 v dd 10 1 v ss 221 dm6, dqs15, tdqs15 12 dq8 132 dq13 42 ???? ? 162 nc , ????? , ?????? , 72 v dd 192 ??? ? 102 ???? 222 nc , ???? ? , ????? ? 13 dq9 133 v ss 43 dqs8 163 v ss 73 ?? ? 193 ?? ? 103 dqs6 223 v ss 14 v ss 134 dm1 , dqs10, tdqs10 44 v ss 164 cb6, nc 74 ??? ? 194 v dd 104 v ss 224 dq54 15 ???? 135 nc , ??? ?? ? ? ???? ?? 45 cb2, nc 165 cb7, nc 75 v dd 195 odt0 105 dq50 225 dq55 16 dqs1 136 v ss 46 cb3, nc 166 v ss 76 ? ? , nc ? 196 a13 106 dq51 226 v ss 17 v ss 137 dq1 4 47 v ss 167 nc (test) 77 odt1 , nc 197 v dd 107 v ss 227 dq60 18 dq 10 138 dq15 48 v tt , nc 168 ????? ? 78 v dd 198 ?? , nc 108 dq56 228 dq61 19 dq 11 139 v ss 49 v tt , nc 169 cke1 /nc 79 ?? , nc 199 v ss 109 dq57 229 v ss 20 v ss 140 dq20 50 cke0 170 v dd 80 v ss 200 dq36 110 v ss 230 dm7, dqs16, tdqs16 21 dq 16 141 dq21 51 v dd 171 a15, nc 81 dq32 201 dq37 111 ???? 231 nc , ???? ? , ????? ? 22 dq 17 142 v ss 52 ba2 172 a14 82 dq33 202 v ss 112 dqs7 232 v ss 23 v ss 143 dm2, dqs11, tdqs11 53 e rr _ o ut , nc 173 v dd 83 v ss 203 dm4 , dqs13, tdqs13 113 v ss 233 dq62 24 ???? 144 nc , ??? ?? ? ? ???? ?? 5 4 v dd 174 a1 2 / ?? 84 ???? 204 nc , ????? , ?????? ? 114 dq58 234 dq63 25 dqs2 145 v ss 55 a11 175 a9 85 dqs4 205 v ss 115 dq59 235 v ss 26 v ss 146 dq22 56 a7 176 v dd 86 v ss 206 dq38 116 v ss 236 v ddspd 27 dq 18 147 dq23 57 v dd 177 a8 87 dq34 207 dq39 117 sa0 237 sa1 28 dq 19 148 v ss 58 a5 178 a6 88 dq35 208 v ss 118 scl 238 sda 29 v ss 149 dq28 59 a4 179 v dd 89 v ss 209 dq44 119 sa2 239 v ss 30 dq 24 150 dq29 60 v dd 18 0 a3 90 dq40 210 dq45 120 v tt 240 v tt note: ck1, ??? , cke1, ?? and odt1 are for 4gb modules only.
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 4 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. input/output functional description symbol type polarity function ck0 , ck1 ??? , ??? input cross point the system clock inputs. all address and command lines are sampled on the cross point of the risi ng edge of ck and falling edge of ?? . a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke0 , cke1 input active high activates the ddr3 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. ?? , ?? input active low enables the associated ddr3 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue, rank 0 is selected by ?? ; rank 1 is selected by ?? ? ??? , ??? , ?? input active low when sampled at the positive rising edge of ck and falling edge of ?? , sign als ??? , ??? , ?? define the operation to be executed by the sdram. odt0, odt1 input active high asserts on - die termination for dq, dm, dqs, and ??? signals if enabled via the ddr3 sdram mode register. dm0 C dm 8 input active high the data write masks, ass ociated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dq s 0 C dq s8 ???? C ???? i/o cross point the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode, the data strobe is sourced by the ddr3 sdram and is sent at the leading edge of the data window. ??? signals are complements, and timing is relative to the cross point of respective dqs and ??? . if the module is to be operated in single ended strobe mode, all ??? signals must be tied on the system board to v ss and ddr3 sdram mode registers programmed appropriately. ba0, ba1, ba2 input - selects which ddr3 sdram internal bank of four or eight is activated. a0 C a9 a10/ap a1 1 a12 / ?? ? a13 - a15 input - during a bank activate command cycle, defines the row address when sampled at the cross point of the risi ng edge of ck and falling edge of ?? . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ?? . in addition to the column address, ap is used to invoke autoprecharge op eration at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0 - ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0 - ban t o control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0 - b a n inputs. if ap is low, then ba0 - b a n are used to define which bank to precharge. dq0 C dq 63 input - data input/output pins. v dd , v ddspd , v s s supply - power supplies for core, i/o, serial presence detect, temp sensor, and ground for the module. v ref dq, v ref ca supply - reference voltage for sstl15 inputs sda i/o - this is a bidirectional pin used to transfer data into or out of the spd eepro m and temp sensor. a resistor must be connected from the sda bus line to v ddspd on the system planar to act as a pull up. scl input - this signal is used to clock data into and out of the spd eeprom and temp sensor. sa0 C sa2 input - address pins used t o select the serial presence detect and temp sensor base address. ????? ? out put - the ????? pin is reserved for use to flag critical module temperature. ????? ? input - this signal resets the ddr3 sdram
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 5 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram [2g b C 1 r ank, 25 6 mx 8 ddr 3 sdrams ] d q 0 d q 1 d q 2 d q 7 d q 4 d q 6 d q 5 d q 3 i / o 0 d 0 n o t e s : 1 . d q - t o - i / o w i r i n g i s s h o w n a s r e c o m m e n d e d b u t m a y b e c h a n g e d . 2 . d q / d q s / d q s / o d t / d m / c k e / s r e l a t i o n s h i p s m u s t b e m a i n t a i n e d a s s h o w n . 3 . f o r e a c h d r a m , a u n i q u e z q r e s i s t o r i s c o n n e c t e d t o g r o u n d . t h e z q r e s i s t o r i s 2 4 0 ? 1 % . 4 . o n e s p d e x i s t s p e r m o d u l e . z q v d d s p d v s s v r e f d q v r e f c a v d d / v d d q s p d d 0 - d 7 d 0 - d 7 d 0 - d 7 b a 0 - b a 2 d 0 - d 7 b a 0 - b a 2 : s d r a m s d 0 - d 7 a 0 - a 1 3 ? ? ? ? ? ? c k e 0 ? ? o d t 0 a 0 - a 1 3 : s d r a m s d 0 - d 7 ? ? ? : s d r a m s d 0 - d 7 ? ? : s d r a m s d 0 - d 7 o d t : s d r a m s d 0 - d 7 ? ? ? : s d r a m s d 0 - d 7 c k e : s d r a m s d 0 - d 7 i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d q 3 2 d q 3 3 d q 3 4 d q 3 9 d q 3 6 d q 3 8 d q 3 7 d q 3 5 i / o 0 d 4 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 0 d q s 0 ? ? ? ? d m 4 d q s 4 ? ? ? ? ? ? d q 8 d q 9 d q 1 0 d q 1 5 d q 1 2 d q 1 4 d q 1 3 d q 1 1 i / o 0 d 1 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 1 d q s 1 ? ? ? ? d q 4 0 d q 4 1 d q 4 2 d q 4 7 d q 4 4 d q 4 6 d q 4 5 d q 4 3 i / o 0 d 5 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 5 d q s 5 ? ? ? ? d q 1 6 d q 1 7 d q 1 8 d q 2 3 d q 2 0 d q 2 2 d q 2 1 d q 1 9 i / o 0 d 2 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 2 d q s 2 ? ? ? ? d q 4 8 d q 4 9 d q 5 0 d q 5 5 d q 5 2 d q 5 4 d q 5 3 d q 5 1 i / o 0 d 6 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 6 d q s 6 ? ? ? ? d q 2 4 d q 2 5 d q 2 6 d q 3 1 d q 2 8 d q 3 0 d q 2 9 d q 2 7 i / o 0 d 3 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 3 d q s 3 ? ? ? ? d q 5 6 d q 5 7 d q 5 8 d q 6 3 d q 6 0 d q 6 2 d q 6 1 d q 5 9 i / o 0 d 7 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 7 d q s 7 ? ? ? ? c k 0 c k : s d r a m s d 0 - d 7 ? ? ? ? ? : s d r a m s d 0 - d 7 ? ? ? ? ? ? ? ? ? ? : s d r a m s d 0 - d 7 d d r 3 s d r a m v t t c k e 0 , a [ 1 3 : 0 ] , ? ? ? , ? ? ? , ? ? , o d t 0 , b a [ 2 : 0 ] , ? ? d d r 3 s d r a m v d d c k ? ? s p d s c l w p s c l s d a s a 0 s a 1 a 0 a 1 a 2
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 6 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram [4g b C 2 r ank s , 256 mx 8 ddr 3 sdrams ] ? ? d m 1 ? ? ? ? d q 8 d q 9 d q 1 0 d q 1 5 d q 1 2 d q 1 4 d q 1 3 d q 1 1 ? ? ? ? d q 1 6 d q 1 7 d q 1 8 d q 2 3 d q 2 0 d q 2 2 d q 2 1 d q 1 9 d m 2 ? ? ? ? d q 2 4 d q 2 5 d q 2 6 d q 3 1 d q 2 8 d q 3 0 d q 2 9 d q 2 7 d m 3 d m 0 ? ? ? ? d q 0 d q 1 d q 2 d q 7 d q 4 d q 6 d q 5 d q 3 d m 5 ? ? ? ? d q s 5 d q 4 0 d q 4 1 d q 4 2 d q 4 7 d q 4 4 d q 4 6 d q 4 5 d q 4 3 d 5 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d m 6 d q s 6 d q s 6 d q 4 8 d q 4 9 d q 5 0 d q 5 5 d q 5 2 d q 5 4 d q 5 3 d q 5 1 d 6 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d m 7 ? ? ? ? d q 5 6 d q 5 7 d q 5 8 d q 6 3 d q 6 0 d q 6 2 d q 6 1 d q 5 9 d 7 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d q s 4 d q 3 2 d q 3 3 d q 3 4 d q 3 9 d q 3 6 d q 3 8 d q 3 7 d q 3 5 d 4 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m ? ? ? ? d m 4 d 1 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 2 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 3 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m c s d q s d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 9 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 1 0 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 1 1 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 8 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 1 3 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 1 4 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 1 5 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 1 2 d q s i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m ? ? d q s 0 d q s 1 d q s 2 d q s 3 c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s c s d q s d q s 7 z q z q z q z q z q z q z q z q z q z q z q z q z q z q z q z q d d r 3 s d r a m v t t c k e [ 1 : 0 ] , a [ 1 3 : 0 ] , ? ? ? , ? ? ? , ? ? , o d t [ 1 : 0 ] , b a [ 2 : 0 ] , ? [ 1 : 0 ] d d r 3 s d r a m v d d c k ? ? v d d s p d v s s v r e f d q v r e f c a v d d / v d d q s p d d 0 - d 1 5 d 0 - d 1 5 d 0 - d 1 5 b a 0 - b a 2 d 0 - d 1 5 b a 0 - b a 2 : s d r a m s d 0 - d 1 5 a 0 - a 1 3 ? ? ? ? ? ? c k e 0 ? ? o d t 0 a 0 - a 1 3 : s d r a m s d 0 - d 1 5 ? ? ? : s d r a m s d 0 - d 1 5 ? ? : s d r a m s d 0 - d 1 5 o d t : s d r a m s d 0 - d 7 ? ? ? : s d r a m s d 0 - d 1 5 c k e : s d r a m s d 0 - d 7 c k 0 c k : s d r a m s d 0 - d 7 ? ? ? ? ? : s d r a m s d 0 - d 7 ? ? ? ? ? ? ? ? ? ? : s d r a m s d 8 - d 1 5 n o t e s : 1 . d q - t o - i / o w i r i n g i s s h o w n a s r e c o m m e n d e d b u t m a y b e c h a n g e d . 2 . d q / d q s / d q s / o d t / d m / c k e / s r e l a t i o n s h i p s m u s t b e m a i n t a i n e d a s s h o w n . 3 . f o r e a c h d r a m , a u n i q u e z q r e s i s t o r i s c o n n e c t e d t o g r o u n d . t h e z q r e s i s t o r i s 2 4 0 ? 1 % . 4 . o n e s p d e x i s t s p e r m o d u l e . s p d s c l w p s c l s d a s a 0 s a 1 a 0 a 1 a 2 d 0 c k e 1 c k e : s d r a m s d 8 - d 1 5 o d t 1 o d t : s d r a m s d 8 - d 1 5 c k 1 c k : s d r a m s d 8 - d 1 5 ? ? ? ? ? : s d r a m s d 8 - d 1 5
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 7 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detect [m2f2g64cb88b7n / m2f2g64cb88b h n , 2gb C 1 rank, 256mx8 ddr3 sdrams] byte description serial pd data entry (hex.) - be - cg - dg 0 crc range, eeprom bytes, bytes used 92 92 93 1 spd revision 10 10 10 2 dram device type 0b 0b 0b 3 module type (form factor) 02 02 02 4 sdram device density and banks 03 03 03 5 sdram device row and column count 19 19 19 6 module minimum nominal voltage 00 00 00 7 module ranks and device dq count 01 01 01 8 ecc tag and module memory bus width 03 03 03 9 fine timebase dividend/divisor (in ps) 52 52 52 10 medium timebase dividend 01 01 01 11 medium timebase di visor 08 08 08 12 minimum sdram cycle time (tckmin) 0f 0c 0a 13 reserved 00 00 00 14 cas latencies supported 1c 3c 7e 15 cas latencies supported 00 00 00 16 minimum cas latency time (taamin) 69 69 64 17 minimum write recovery time (twrmin) 78 78 78 18 minimum cas - to - cas delay (trcdmin) 69 69 64 19 minimum row active to row active delay (trrdmin) 3c 30 30 20 minimum row precharge delay (trpmin) 69 69 64 21 upper nibble for tras and trc 11 11 11 22 minimum active - to - precharge delay (trasmin) 2c 20 18 23 minimum active - to - active/refresh delay (trcmin) 95 89 7c 24 minimum refresh recovery delay (trfcmin) lsb 00 00 00 25 minimum refresh recovery delay (trfcmin) msb 05 05 05 26 minimum internal write - to - read command delay (twtrmin) 3c 3c 3c 27 mini mum internal read - to - precharge command delay (trtpmin) 3c 3c 3c 28 minimum four active window delay (tfawmin) lsb 01 00 00 29 minimum four active window delay (tfawmin) msb 2c f0 f0 30 sdram device output drivers supported 83 83 83 31 sdram device ther mal and refresh options 05 05 05 32 module thermal sensor 00 00 00 33 sdram device type 00 00 00 60 module height (nominal) 0f 0f 0f 61 module thickness (max) 01 01 01 62 raw card id reference 01 01 01 63 dram address mapping edge connector 01 01 01 117 module manufacture id 83 83 83 118 module manufacture id 0b 0b 0b 119 - 121 module manufacturer information -- -- -- 126 crc 47 05 fb 127 crc 29 80 32 128 - 145 module part number -- -- -- 146 module die revision -- -- -- 147 module pcb revision -- -- -- 150 - 175 manufacturer reserved -- -- -- 176 - 255 intel extreme memory profile (xmp) -- -- --
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 8 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detect [m2f 4 g64cb8 h b 5 n / m2f 4 g64cb8 h b 9 n , 4 gb C 2 rank s , 256mx8 ddr3 sdrams] byte description serial pd data entry (hex.) - be - cg - d g 0 crc range, eeprom bytes, bytes used 92 92 93 1 spd revision 10 10 10 2 dram device type 0b 0b 0b 3 module type (form factor) 02 02 02 4 sdram device density and banks 03 03 03 5 sdram device row and column count 19 19 19 6 module minimum nominal voltage 00 00 00 7 module ranks and device dq count 09 09 09 8 ecc tag and module memory bus width 03 03 03 9 fine timebase dividend/divisor (in ps) 52 52 52 10 medium timebase dividend 01 01 01 11 medium timebase divisor 08 08 08 12 minimum sdram c ycle time (tckmin) 0f 0c 0a 13 reserved 00 00 00 14 cas latencies supported 1c 3c 7e 15 cas latencies supported 00 00 00 16 minimum cas latency time (taamin) 69 69 64 17 minimum write recovery time (twrmin) 78 78 78 18 minimum cas - to - cas delay (trcdm in) 69 69 64 19 minimum row active to row active delay (trrdmin) 3c 30 30 20 minimum row precharge delay (trpmin) 69 69 64 21 upper nibble for tras and trc 11 11 11 22 minimum active - to - precharge delay (trasmin) 2c 20 18 23 minimum active - to - active/re fresh delay (trcmin) 95 89 7c 24 minimum refresh recovery delay (trfcmin) lsb 00 00 00 25 minimum refresh recovery delay (trfcmin) msb 05 05 05 26 minimum internal write - to - read command delay (twtrmin) 3c 3c 3c 27 minimum internal read - to - precharge com mand delay (trtpmin) 3c 3c 3c 28 minimum four active window delay (tfawmin) lsb 01 00 00 29 minimum four active window delay (tfawmin) msb 2c f0 f0 30 sdram device output drivers supported 83 83 83 31 sdram device thermal and refresh options 05 05 05 32 module thermal sensor 00 00 00 33 sdram device type 00 00 00 60 module height (nominal) 0f 0f 0f 61 module thickness (max) 11 11 11 62 raw card id reference 01 01 01 63 dram address mapping edge connector 01 01 01 117 module manufacture id 83 83 8 3 118 module manufacture id 0b 0b 0b 119 - 121 module manufacturer information -- -- -- 126 crc 68 2a d4 127 crc 59 f0 42 128 - 145 module part number -- -- -- 146 module die revision -- -- -- 147 module pcb revision -- -- -- 150 - 175 manufacturer reser ved -- -- -- 176 - 255 intel extreme memory profile (xmp) -- -- --
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 9 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. environmental requirements symbol parameter rating units note t opr module operating temperature range (ambient) 0 to 55 c 3 h opr operating humidity (relative) 10 to 90 % 1 t stg storage temperature (plastic) - 55 to 100 c 1 h stg storage humidity (without condensation) 5 to 95 % 1 p bar barometric pressure (operating & storage) 105 to 69 k pascal 1, 2 note : 1 . stresses greater than those listed may cause permanent damage to t he device. this is a s tress rating only and device functional operation at or above the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect reliability. 2. up to 9850 ft . 3. the component max imum case temperature shall not exceed the value specified in the component spec. absolute maximum dc ratings symbol parameter rating units note v dd voltage on vdd pins relative to vss - 0.4 v ~ 1.975 v v 1, 3 v dd q voltage on vddq pins relative to vss - 0.4 v ~ 1.975 v v 1, 3 v in , v out voltage on i/o pins relative to vss - 0.4 v ~ 1.975 v v 1 t stg storage temperature - 55 to +100 c 1, 2 note : 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device . this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended perio ds may affect reliability 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51 - 2 standard. 3. vdd and vddq must be within 300 mv of each other at all times;and vre f must be not greater operating temperature conditions symbol parameter rating units note t op e r normal operating temperature range 0 to 85 c 1, 2 extended temperature range 85 to 95 c 1, 3 note: 1. operating temperature toper is the case surface t emperature on the center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51 - 2. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 to 85 c under all operating conditions 3. some applications require operation of the dram in the extended temperature range between 85 c and 95 c case temperature. full specifications are supported in this range, but the following additional conditions apply: a ) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extended tem perature range. please refer to supplier data sheet and/or the dimm spd for option availability. b ) if self - refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self - refresh mode with extended tempe rature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self - refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). please refer to the supplier data sheet and/or the dimm spd for auto self - refresh option availability, extended temperature r ange support and trefi requirements in the extended temperature range.
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 10 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. dc electrical characteristics and operating conditions symbol parameter min typ max units notes v dd supply voltage 1.425 1.5 1.575 v 1,2 v dd q output supply voltage 1.425 1.5 1.5 75 v 1,2 note: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. single - ended ac and dc input levels for command and address symbol parameter ddr3 - 1066 ( - be) ddr3 - 1333 ( - cg) ddr3 - 1600( - d i ) units note min. max. min. max. min. max. v ih.ca(dc) dc input logic high vref + 0.100 vdd vref + 0.100 vdd vref + 0.100 vdd v 1 v il.ca(dc) dc input logic low vss vref - 0.100 vss vref - 0.100 vss vref - 0.100 v 1 v ih.ca(ac) ac input logic high vref + 0.175 note 2 vref + 0.175 note 2 vref + 0.175 note 2 v 1, 2 v il.ca(ac) ac input logic low note 2 vref - 0.175 note 2 vref - 0.175 note 2 vref - 0.175 v 1, 2 v ih.ca(ac150) ac input logic high vref + 0.15 note 2 vref + 0.15 note 2 vref + 0.15 note 2 v 1, 2 v il.ca(ac150) ac input logic low note 2 vref - 0.15 note 2 vref - 0.15 note 2 vref - 0.15 v 1, 2 v ref ca (dc) reference voltage for add, cmd inputs 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd v 3 , 4 note: 1. for input only pins except reset#. vref = vrefca(dc). 2. s ee overshoot and unders hoot specifications in the device datasheet . 3. the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd (for reference: approx. +/ - 15 mv). 4. for reference: approx. vdd/2 +/ - 15 mv. single - ended ac and dc input levels for dq and dm symbol parameter ddr3 - 1066 ( - be) ddr3 - 1333 ( - cg) ddr3 - 1600 ( - d i ) units note min. max. min. max. min. max. v ih.dq(dc) dc input logic h igh vref + 0.100 vdd vref + 0.100 vdd vref + 0.100 vdd v 1 v il.dq(dc) dc input logic low vss vref - 0.100 vss vref - 0.100 vss vref - 0.100 v 1 v ih.dq(ac) ac input logic high vref + 0.175 note 2 vref + 0.15 note 2 vref + 0.15 note 2 v 1, 2, 5 v il.dq(ac) ac input logic low note 2 vref - 0.175 note 2 vref - 0.15 note 2 vref - 0.15 v 1, 2, 5 v refdq(dc) reference voltage for dq, dm inputs 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd v 3, 4 note: 1. for input only pins except reset#. v ref = vrefdq(dc). 2. s ee overshoot and unders hoot specifications in the device datasheet . 3. the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd (for reference: approx. +/ - 15 mv). 4. for reference: approx. vdd/ 2 +/ - 15 mv. 5. single - ended swing requirement for dqs, dqs# is 350 mv (peak to peak). differential swing requirement for dqs - dqs# is 700 mv (peak to peak).
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 11 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1. 5 v 0. 075 v [2g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 pc3 - 1 28 00 unit ( - be) ( - cg) ( - d i ) idd0 operating one bank active - precharge current 577 579 609 ma idd1 operating one bank active - read - precharge current 725 750 790 ma idd2p 0 precharge power - down current slow exit 33 48 51 ma idd2p1 precharge power - down current fast exit 104 132 143 ma idd2q precharge quiet standby current 167 204 185 ma idd2n precharge standby current 182 220 243 ma idd3p active power - down current 114 14 4 158 ma idd3n active standby current 236 231 255 ma idd4r operating burst read current 1011 1302 1510 ma idd4w operating burst write current 1028 1239 1438 ma idd5b burst refresh current 1531 1507 1531 ma idd6 self refresh current: normal temperatur e range 83 56 56 ma idd7 operating bank interleave read current 2590 2997 3062 ma operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1. 5 v 0. 075 v [ 4 g b C 2 r ank s , 256 mx 8 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 pc3 - 1 28 00 unit ( - be) ( - cg) ( - d i ) idd0 operating one bank active - precharge current 813 810 864 ma idd1 operating one bank active - read - precharge current 961 980 1045 ma idd2p0 precharge power - down current slow exit 66 95 102 ma idd2p1 precharge powe r - down current fast exit 209 264 285 ma idd2q precharge quiet standby current 333 408 370 ma idd2n precharge standby current 364 440 486 ma idd3p active power - down current 228 289 317 ma idd3n active standby current 472 461 510 ma idd4r operating burs t read current 1247 1533 1765 ma idd4w operating burst write current 1264 1470 1693 ma idd5b burst refresh current 1767 1737 1786 ma idd6 self refresh current: normal temperature range 167 113 113 ma idd7 operating bank interleave read current 2826 32 28 3318 ma
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 12 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. standard speed bins ddr3 - 1066 mhz speed bin ddr3 - 1066 unit cl - nrcd - nrp 7 - 7 - 7 ( - be) parameter symbol min max internal read command to first data taa 13.125 20 ns act to internal read or write delay time trcd 13.125 - ns pre command pe riod trp 13.125 - ns act to act or ref command period trc 50.625 - ns act to pre command period tras 37.5 9*trefi ns cl=5 cwl=5 tck(avg) 3 3 .3 ns cwl=6 tck(avg) reserved ns cl=6 cwl=5 tck(avg) 2.5 3. 3 ns cwl=6 tck(avg) reserved ns cl=7 cwl=5 tck (avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cl=8 cwl=5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns supported cl settings 5, 6,7,8 nck supported cwl settings 5,6 nck ddr3 - 1333mhz speed bin ddr3 - 1333 unit cl - nrcd - nrp 9 - 9 - 9 ( - cg) parame ter symbol min max internal read command to first data taa 13. 125 20.000 ns act to internal read or write delay time trcd 13. 125 - ns pre command period trp 13. 125 - ns act to act or ref command period trc 49. 125 - ns act to pre command period t ras 36 9*trefi ns cl=5 cwl=5 tck(avg) 3 3.3 ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cl=6 cwl=5 tck(avg) 2.5 3.3 ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cl=7 cwl=5 tck(avg) res erved reserved ns cwl=6 tck(avg) 1.875 * <2.5 * ns cwl=7 tck(avg) reserved reserved ns cl=8 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved reserved ns cl=9 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(a vg) reserved reserved ns cwl=7 tck(avg) 1.5 <1.875 ns cl=10 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.5 * <1.875 * ns supported cl settings 5, 6,7 * ,8,9 ,10* nck supported cwl settings 5,6,7 nck
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 13 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ddr3 - 1 600 mhz speed bin ddr3 - 1 600 unit cl - nrcd - nrp 11 - 11 - 11 ( - d i ) parameter symbol min max internal read command to first data taa 13.125 20 ns act to internal read or write delay time trcd 13.125 - ns pre command period trp 13.125 - ns act to act or re f command period trc 4 8.125 - ns act to pre command period tras 3 5 9*trefi ns cl=5 cwl=5 tck(avg) 3 3.3 ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cl=6 cwl=5 tck(avg) 2.5 3.3 ns cwl=6 tck(avg) 1.875 * <2.5 * ns cwl= 7 tck(avg) reserved reserved ns cl=7 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 * <2.5 * ns cwl=7 tck(avg) reserved reserved ns cl=8 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) 1.5 <1.875 ns cl=9 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.500 <1.875 ns cl=10 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.500 * <1.875 * ns supported cl settings 5, 6,7 * ,8, 9 *,10, 11 nck supported cwl settings 5,6,7 ,8 nck *: optional
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 14 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing speci fi cations for ddr 3 sdram devices used on module (1066mhz) parameter symbol ddr3 - 1 066 units notes min. max. clock timing minimum clock cycle time (d ll off mode) tck (dll_off) 8 - ns average clock period tck(avg) refer to "standard speed bins) ps average high pulse width tch(avg) 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck( avg)min + tjit(per)min max.: tck(avg)max + tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - tck(avg) clock period jitter jit(per) - 90 90 ps clock period jitter during dll lo cking period jit(per, lck) - 80 80 ps cycle to cycle period jitter tjit(cc) 180 180 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 160 160 ps duty cycle jitter tjit(duty) - - ps cumulative error across 2 cycles terr(2per) - 132 132 ps cumulative error across 3 cycles terr(3per) - 157 157 ps cumulative error across 4 cycles terr(4per) - 175 175 ps cumulative error across 5 cycles terr(5per) - 188 188 ps cumulative error across 6 cycles terr(6per) - 200 200 ps cumu lative error across 7 cycles terr(7per) - 209 209 ps cumulative error across 8 cycles terr(8per) - 217 217 ps cumulative error across 9 cycles terr(9per) - 224 224 ps cumulative error across 10 cycles terr(10per) - 231 231 ps cumulative error acros s 11 cycles terr(11per) - 237 237 ps cumulative error across 12 cycles terr(12per) - 242 242 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min terr(nper)max = (1 + 0.68ln(n)) * tjit(per )max ps data timing dqs, dqs# to dq skew, per group, per access tdqsq - 150 ps dq output hold time from dqs, dqs# tqh 0.38 - tck(avg) dq low - impedance time from ck, ck# tlz(dq) - 600 300 ps dq high impedance time from ck, ck# thz(dq) - 3 00 ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 25 ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds( base) ac150 75 ps data hold time from dqs, dqs# referenced to vih(dc) / vil(d c) levels tdh(base) dc100 100 ps dq and dm input pulse width for each input tdipw 490 ps data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 tck(avg) dqs, dqs# differential read postamble trpst 0.3 note 11 tck(avg) dqs, dqs# differential output high time tqsh 0.38 - tck(avg) dqs, dqs# differential output low time tqsl 0.38 - tck(avg) dqs, dqs# differential write preamble twpre 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - tck(avg) dq s, dqs# rising edge output access time from rising ck, ck# tdqsck - 300 300 tck(avg) dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 600 300 tck(avg) dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 300 tck( avg) dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 tck(avg) dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 tck(avg) dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.25 0.25 tck(avg) dqs, dqs# falling edge setu p time to ck, ck# rising edge tdss 0.2 - tck(avg) dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - tck(avg) command and address timing dll locking time tdllk 512 - nck
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 15 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. internal read command to precharge command delay tr tp trtpmin.: max(4nck, 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - ns mode register set command cycle time tmrd 4 - nck m ode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd pre command period trp act to act or ref command period trc cas# to cas# command delay tccd 4 - nck a uto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - nck active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd max(4nck, 7.5ns) - active to active command period for 2kb page size trrd trrdmin.: max(4nck, 10ns) trrdmax.: four activate window for 1kb page size tfaw 37.5 - ns four activate window for 2kb page size tfaw 50 - ns command and ad dress setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 125 - ps command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 200 - ps command and address setup time to ck, ck# referenced to vih( ac) / vil(ac) levels tis(base) ac150 125+150 - ps control and address input pulse width for each input tipw 780 - ps calibration timing power - up and reset calibration time tzqinit 512 - nck normal operation full calibration time tzqoper 25 6 - nck normal operation short calibration time tzqcs 64 - nck reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands no t requiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing tckesr tck esrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down ex it (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max( 3nck, 7.5ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck 5.625 ns) tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 tcpdedmin.: - nck power down entry to exit timing tpd tpdmin.: tcke(min) tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 tactpdenmax.: - nck timing of pre or prea command to power down entry tprpden tprpdenmin.: 1 tprpdenmax.: - nck timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 16 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / t ck(avg)) twrpdenmax.: - nck timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twr pdenmax.: - nck timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry trefpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command to power dow n entry tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write command and bl8 odth8 odth8min.: 6 odth8max .: - nck asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 ns rtt turn - on taon - 300 300 ps rtt_nom and rtt_wr turn - off time from odtloff refe rence taof 0.3 0.7 tck(avg) rtt dynamic change skew tadc 0.3 0.7 tck(avg) write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - nck dqs/dqs# delay after write leveling mode is programmed tw ldqsen 25 - nck write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 245 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 245 - ps write leveling output delay twlo 0 9 ns write leveling output error twloe 0 2 ns
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 17 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing speci fi cations for ddr 3 sdram devices used on module (1333mhz) parameter symbol ddr3 - 1333 units notes min. max. clock timing minimum clock cycle time (dll off mode) tck (dll_of f) 8 - ns average clock period tck(avg) refer to "standard speed bins) ps average high pulse width tch(avg) 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min m ax.: tck(avg)max + tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - tck(avg) clock period jitter jit(per) - 80 80 ps clock period jitter during dll locking period jit(per, lc k) - 70 70 ps cycle to cycle period jitter tjit(cc) 160 160 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 140 140 ps duty cycle jitter tjit(duty) - - ps cumulative error across 2 cycles terr(2per) - 118 118 ps cumulati ve error across 3 cycles terr(3per) - 140 140 ps cumulative error across 4 cycles terr(4per) - 155 155 ps cumulative error across 5 cycles terr(5per) - 168 168 ps cumulative error across 6 cycles terr(6per) - 177 177 ps cumulative error across 7 cy cles terr(7per) - 186 186 ps cumulative error across 8 cycles terr(8per) - 193 193 ps cumulative error across 9 cycles terr(9per) - 200 200 ps cumulative error across 10 cycles terr(10per) - 205 205 ps cumulative error across 11 cycles terr(11per) - 210 210 ps cumulative error across 12 cycles terr(12per) - 215 215 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max ps data timing dqs, dqs# to dq skew, per group, per access tdqsq - 125 ps dq output hold time from dqs, dqs# tqh 0.38 - tck(avg) dq low - impedance time from ck, ck# tlz(dq) - 500 250 ps dq high impedance time from ck, ck# thz(dq) - 250 ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 - ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds( base) ac150 30 ps data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 65 ps dq and dm input pulse width for each input tdipw 400 - ps data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 tck(avg) dqs, dqs# differential read postamble trpst 0.3 note 11 tck(avg) dqs, dqs# differential output high time tqsh 0.4 - tck(avg) dqs, dqs# differential output low time tqsl 0.4 - tck(avg) dqs, dqs# differential write preamble twpre 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - tck(avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 255 255 tck(avg) dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 500 250 tck(avg) dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 250 tck(avg) dqs, dqs# different ial input low pulse width tdqsl 0.45 0.55 tck(avg) dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 tck(avg) dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.25 0.25 tck(avg) dqs, dqs# falling edge setup time to ck, ck# rising ed ge tdss 0.2 - tck(avg) dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - tck(avg) command and address timing
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 18 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. dll locking time tdllk 512 - nck internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5n s) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - ns mode register set command cycle time tmrd 4 - nck mode register set command up date delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd pre command period trp act to act or ref command period trc cas# to cas# command delay tccd 4 nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - nck active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd trrdmin.: max(4nck , 6ns) trrdmax.: active to active command period for 2kb page size trrd trrdmin.: max(4nck, 7.5ns) trrdmax.: four activate window for 1kb page size tfaw 30 0 ns four activate window for 2kb page size tfaw 45 0 ns command and address setup t ime to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 65 - ps command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 140 - ps command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac150 65+125 - ps control and address input pulse width for each input tipw 620 - ps calibration timing power - up and reset calibration time tzqinit 512 - nck normal operation full calibration time tzqoper 256 - nck nor mal operation short calibration time tzqcs 64 - nck reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a l ocked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(m in) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or res et exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 6 ns) txpm ax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck ,5.625 ns) tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 tcpdedmin.: - nck power down entry to exit timing tpd tpdmin.: tcke(min) tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 tactpdenmax.: - nck timing of pre or prea command to power down entry tpr pden tprpdenmin.: 1 nck
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 19 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. tprpdenmax.: - timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) twrpd enmax.: - nck timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twrpdenmax.: - nc k timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry trefpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command to power down entry tmrspd en tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write command and bl8 odth8 odth8min.: 6 odth8max.: - nck as ynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 ns rtt turn - on taon - 250 250 ps rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 tck(avg) rtt dynamic change skew tadc 0.3 0.7 tck(avg) write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - nck dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - nck write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 195 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 195 - ps write leveling output delay twlo 0 9 ns write leveling output error twloe 0 2 ns
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 20 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing speci fi cations for ddr 3 sdram devices used on module (1600mhz) parameter symbol ddr3 - 1600 units notes min. max. clock timing minimum clock cycle time (dll off mode) tck (dll_off) 8 - ns av erage clock period tck(avg) refer to "standard speed bins) ps average high pulse width tch(avg) 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min max.: tck(avg)ma x + tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - tck(avg) clock period jitter jit(per) - 7 0 7 0 ps clock period jitter during dll locking period jit(per, lck) - 6 0 6 0 ps cycle to cycle period jitter tjit(cc) 140 1 4 0 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 1 2 0 1 2 0 ps duty cycle jitter tjit(duty) - - ps cumulative error across 2 cycles terr(2per) - 103 103 ps cumulative error across 3 cycles terr(3per) - 1 22 122 ps cumulative error across 4 cycles terr(4per) - 1 36 1 36 ps cumulative error across 5 cycles terr(5per) - 1 47 1 47 ps cumulative error across 6 cycles terr(6per) - 1 55 1 55 ps cumulative error across 7 cycles terr(7per) - 1 63 1 63 ps cumulative error across 8 cycles terr(8per) - 1 69 1 69 ps cumulative error across 9 cycles terr(9per) - 175 175 ps cumulative error across 10 cycles terr(10per) - 180 180 ps cumulative error across 11 cycles terr(11per) - 184 184 ps cumulative error across 12 cycles terr(12per) - 188 188 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max ps data timing dqs, dqs # to dq skew, per group, per access tdqsq - 100 ps dq output hold time from dqs, dqs# tqh 0.38 - tck(avg) dq low - impedance time from ck, ck# tlz(dq) - 450 2 2 5 ps dq high impedance time from ck, ck# thz(dq) - 2 2 5 ps data setup time to dqs, dqs# r eferenced to vih(ac) / vil(ac) levels tds(base) ac175 - ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds( base) ac150 10 ps data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 4 5 ps dq a nd dm input pulse width for each input tdipw 36 0 - ps data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 tck(avg) dqs, dqs# differential read postamble trpst 0.3 note 11 tck(avg) dqs, dqs# differential output high tim e tqsh 0.4 - tck(avg) dqs, dqs# differential output low time tqsl 0.4 - tck(avg) dqs, dqs# differential write preamble twpre 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - tck(avg) dqs, dqs# rising edge output access time fro m rising ck, ck# tdqsck - 255 255 tck(avg) dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 450 2 2 5 tck(avg) dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 225 tck(avg) dqs, dqs# differential input low p ulse width tdqsl 0.45 0.55 tck(avg) dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 tck(avg) dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.2 7 0.2 7 tck(avg) dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0. 18 - tck(avg) dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0. 18 - tck(avg) command and address timing
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 21 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. dll locking time tdllk 512 - nck internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - ns mode register set command cycle time tmrd 4 - nck mode register set command update delay tm od tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd pre command period trp act to act or ref command period trc cas# to cas# command delay tccd 4 nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - nck active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd trrdmin.: max(4nck, 6ns) trrdma x.: active to active command period for 2kb page size trrd trrdmin.: max(4nck, 7.5ns) trrdmax.: four activate window for 1kb page size tfaw 30 - ns four activate window for 2kb page size tfaw 4 0 - ns command and address setup time to ck, ck # referenced to vih(ac) / vil(ac) levels tis(base) 45 - ps command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 1 2 0 - ps command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(ba se) ac150 170 - ps control and address input pulse width for each input tipw 560 - ps calibration timing power - up and reset calibration time tzqinit 512 - nck normal operation full calibration time tzqoper 256 - nck normal operation sh ort calibration time tzqcs 64 - nck reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll txs tx smin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tcke srmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit tcksrx t cksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 6 ns) txpmax.: - exi t precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck ,5 ns) tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 tcpded min.: - nck power down entry to exit timing tpd tpdmin.: tcke(min) tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 tactpdenmax.: - nck timing of pre or prea command to power down entry tprpden tprpdenmin.: 1 nck
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 22 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. tprpdenmax.: - timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) twrpdenmax.: - nck tim ing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twrpdenmax.: - nck timing of wra c ommand to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry trefpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command to power down entry tmrspden tmrspdenmin.: tmo d(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write command and bl8 odth8 odth8min.: 6 odth8max.: - nck asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 ns rtt turn - on taon - 2 25 2 25 ps rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 tck(avg) rtt dynamic change skew tadc 0.3 0.7 tck(avg) write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - nck dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - nck write leveling s etup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 1 6 5 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 1 6 5 - ps write leveling output delay twlo 0 7.5 ns write leveling output er ror twloe 0 2 ns
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 23 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [ m2f(x)2g64cb88b7n , 2g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b 0 . 8 0 + / - 0 . 0 5 b a c k 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h d e t a i l a 9 . 5 0 1 3 3 . 3 5 + / - 0 . 1 5 u n i t s : m i l l i m e t e r s 3 0 . 0 0 + 0 . 5 / - 0 . 1 5 s i d e 2 . 7 m a x . 1 . 2 7 + / - 0 . 1 0 1 7 . 3 0 5 . 1 7 5 4 7 . 0 0 d e t a i l b 7 1 . 0 0 5 . 0 0 2 . 5 0 3 . 0 ( x 4 )
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 24 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. [ m2f 2g64cb88bhn , 2g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b 0 . 8 0 + / - 0 . 0 5 b a c k 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h d e t a i l a 9 . 5 0 1 3 3 . 3 5 + / - 0 . 1 5 u n i t s : m i l l i m e t e r s 3 0 . 0 0 + 0 . 5 / - 0 . 1 5 s i d e 4 . 3 0 m a x . 1 . 2 7 + / - 0 . 1 1 7 . 3 0 5 . 1 7 5 4 7 . 0 0 d e t a i l b 7 1 . 0 0 5 . 0 0 2 . 5 0 2 5 . 0 0 + / - 0 . 2 1 2 6 + / - 0 . 2
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 25 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [ m2f 4g64cb8hb5 n , 4 g b C 2 r ank s , 256 mx 8 ddr 3 sdra ms ] note: device position and scale are only for reference. f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b 0 . 8 0 + / - 0 . 0 5 b a c k 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h d e t a i l a 9 . 5 0 1 3 3 . 3 5 + / - 0 . 1 5 u n i t s : m i l l i m e t e r s 3 0 . 0 0 + 0 . 5 / - 0 . 1 5 s i d e 4 . 0 0 m a x . 1 . 2 7 + / - 0 . 1 0 1 7 . 3 0 5 . 1 7 5 4 7 . 0 0 d e t a i l b 7 1 . 0 0 5 . 0 0 2 . 5 0 3 . 0 ( x 4 )
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 26 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. [ m2f 4g64cb8hb9n , 4 g b C 2 r ank s , 256 mx 8 ddr 3 sdra ms ] f r o n t 1 . 5 0 + / - 0 . 1 0 d e t a i l a d e t a i l b 0 . 8 0 + / - 0 . 0 5 b a c k 3 . 8 0 4 . 0 0 1 . 0 0 p i t c h d e t a i l a 9 . 5 0 1 3 3 . 3 5 + / - 0 . 1 5 u n i t s : m i l l i m e t e r s 3 0 . 0 0 + 0 . 5 / - 0 . 1 5 s i d e 5 . 6 0 m a x 1 . 2 7 + / - 0 . 1 1 7 . 3 0 5 . 1 7 5 4 7 . 0 0 d e t a i l b 7 1 . 0 0 5 . 0 0 2 . 5 0 1 2 6 . 0 0 + / - 0 . 2 2 5 . 0 0 + / - 0 . 2
m2f2g64cb88b7n / m2f4g64cb8hb5n M2F2G64CB88BHN / m2f4g6 4cb8hb9n 2g b: 256m x 64 / 4gb: 512m x 64 pc3 - 85 00 / pc3 - 10600 /pc - 12800 unbuffered ddr 3 sdram dimm rev 1.1 27 1 0 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. revision log rev date mod ification 0.1 01/2010 preliminary release 0.5 0 5 /2010 preliminary release 2 1.0 0 6 /2010 official release 1.1 10/2010 revision update (re - move over - clocking products)

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